In this paper, we present our quantitative studies of the impact of 3D IC design on repeater usage. The repeater usage is estimated by the interconnect optimizer IPEM in the post-placement/pre-routing stage, where the 2D and 3D placement are generated by state-of-art mixed-size placers mPL6 and mPL-3D. Experiments on a set of real industrial designs show that, through 3D placement, the total number of repeaters used in the on-chip interconnections can be reduced by 19.74% and 51.41% on average with 3 layers and 4 layers of 3D IC designs, respectively.