This paper will present work on a recharged com-parator using Semi Floating-Gate (SFG) MOS devices. The output voltage of a basic SFG MOS Comparator circuit is normally interleaved with a recharge voltage. This prohibit control of passgates, which requires binary control signals. An output buffer is introduced to allow the control of pass-gates and multiplexers (MUXs) beyond a single recharge clock period. The recharged comparator is utilized as reset logic in a recharged multiplevalued (MV) n-ary frequency divider (FDIV). The MV FDIV reduces the number of transistors required for a configurable frequency division of modulus between two and eight. This makes it applicable as bit-counter and symbol clock generator in recharged configurable serial D/A converters. Simulation data is obtained using AMS 0.35µm process parameters c35b4.