… weak rows, how would one design a practical and energy-efficient mechanism that
enables finegrained refresh control without intrusive device changes. Proposed REFLEX …

… CBR refresh is performed, the device refreshes … Refresh technique is suited to RAS-only
Refresh, and despite the overhead over CBR, RAS-only refresh method with our Smart Refresh …

… Hence, the information we collect and use in RIO and PARIS will be extremely useful to
control self refresh power. Pursuing this direction requires major changes in the DRAM interface, …

… For devices with multiple refresh rates, we employ a more robust scheme where SYNC and
END have distinct refresh … refresh rate to multiple bits if the device has a sufficient number of …

… in future DRAM devices as DRAM capacity increases [3… make refresh unnecessary by
ensuring that the row to be refreshed is accessed at the same time it is supposed to be refreshed. …

… The negative effects of DRAM refresh increase as DRAM device capacity increases.
Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device. …

… 3) Based on full-system simulations, we demonstrate the refresh penalties versus device
speed, device size, and total memory size. We also show that as the total memory capacity …

… As DRAM devices become denser, the time taken to complete … refresh, we utilized an internal
refresh counter inside the DRAM. The refresh counter tracks the set of rows to be refreshed …

… This is simply handled by refreshing multiple rows for each refresh pulse. For example, for
the 8Gb device we consider, there are 8 rows per Refresh Bundle. When the DRAM array gets …

… Third, the Operating System (OS) configures the DRAM self-refresh counter before switching
to the self-refresh mode. Finally, the self-refresh controller refreshes different rows of the …