This paper focuses on a review of state-of-the-art memory designs and new design methods
for near-threshold computing (NTC). In particular, it presents new ways to design reliable
low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a
digital wrapper around existing commercially available memories. The approach is based
on modeling at system level supported by silicon measurement on a test chip in a 40nm low-
power processing technology. Advanced monitoring, control and run-time error mitigation …