Robust low-power CMOS precharge logic
O Mirmotahari, Y Berg - 2013 IEEE Faible Tension Faible …, 2013 - ieeexplore.ieee.org
2013 IEEE Faible Tension Faible Consommation, 2013•ieeexplore.ieee.org
In this paper we improve the Ultra Low-Voltage gate by including a keeper transistor at the
floating-gate to make the gate more static. Thus, the refresh overhead is excluded, in
addition the power consumption in evaluation period is significant lower. We also evaluate
the gates behaviour for the effect of delayed input signal. All results are obtained by
simulation in Cadence for a 90 nm process parameters.
floating-gate to make the gate more static. Thus, the refresh overhead is excluded, in
addition the power consumption in evaluation period is significant lower. We also evaluate
the gates behaviour for the effect of delayed input signal. All results are obtained by
simulation in Cadence for a 90 nm process parameters.
In this paper we improve the Ultra Low-Voltage gate by including a keeper transistor at the floating-gate to make the gate more static. Thus, the refresh overhead is excluded, in addition the power consumption in evaluation period is significant lower. We also evaluate the gates behaviour for the effect of delayed input signal. All results are obtained by simulation in Cadence for a 90 nm process parameters.
ieeexplore.ieee.org
以上显示的是最相近的搜索结果。 查看全部搜索结果