Semiconductor memory device having different substrate thickness between memory cell area and peripheral area and manufacturing method thereof
JW Yang - US Patent 5,930,648, 1999 - Google Patents
57 ABSTRACT A Semiconductor memory device is provided with a Semi conductor
Substrate having a lower Semiconductor layer, an upper Semiconductor layer and a buried
insulation layer interposed therebetween. wherein the upper Semiconductor layer has a first
and a Second regions and a thickness of the first region is Smaller than that of the Second
region; a memory cell area including a plurality of memory cell elements formed on the first
region; and a peripheral circuit area including a plurality of peripheral circuit elements …
Substrate having a lower Semiconductor layer, an upper Semiconductor layer and a buried
insulation layer interposed therebetween. wherein the upper Semiconductor layer has a first
and a Second regions and a thickness of the first region is Smaller than that of the Second
region; a memory cell area including a plurality of memory cell elements formed on the first
region; and a peripheral circuit area including a plurality of peripheral circuit elements …
以上显示的是最相近的搜索结果。 查看全部搜索结果