基于摆幅恢复传输管逻辑的高性能全加器设计
韩金亮， 张跃军， 温亮， 张会红 - 工程科学学报, 2020 - cje.ustb.edu.cn
… full adder circuit, we proposed a full adder design scheme based on swing restored pass-transistor …
the designed XOR/XNOR circuit to the full adder structure and used the 4T XOR sum …
the designed XOR/XNOR circuit to the full adder structure and used the 4T XOR sum …
用于图像融合基于混合全加器和计数器的高效华莱士树型乘法器
… An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for … full
adder by exploring new XOR and XNOR gates. IEEE Trans Very Large Scale Integr Syst, 26(8…
adder by exploring new XOR and XNOR gates. IEEE Trans Very Large Scale Integr Syst, 26(8…
[PDF][PDF] 基于忆阻器的乘法器电路设计
王光义， 沈书航， 刘公致， 李付鹏 - 电子与信息学报, 2020 - jeit.ac.cn
… mainly involve the research of full adder, multiplier, exclusive-OR (XOR) and equivalence
(XNOR), etc., … An improved memristor-CMOS XOR logic gate and a novel full adder[C]. The 9th …
(XNOR), etc., … An improved memristor-CMOS XOR logic gate and a novel full adder[C]. The 9th …
量子点细胞自动机中四值逻辑门的设计与模拟新概念
… In this paper, we propose a novel creative concept for quaternary QCA (QQCA). The concept
… gates are compared with quaternary gates based on carbon nanotube field-effect transistor (…
… gates are compared with quaternary gates based on carbon nanotube field-effect transistor (…
[PDF][PDF] 存算一体电路与跨层次协同设计优化: 从SRAM 到铁电晶体管
尹勋钊， 岳金山， 黄庆荣， 李超， 蔡嘉豪… - 中国科学: 信息 …, 2022 - scis.scichina.com
… 1-bit full adder; (b) SRAM cell with 1-bit multiplier and adder … 此外, 对于二值化同或 (not
exclusive or, XNOR) 神经网络, 其… 普遍能够支持4/8 bit 或更加丰富的计算位宽, 并且在4 bit 位宽下…
exclusive or, XNOR) 神经网络, 其… 普遍能够支持4/8 bit 或更加丰富的计算位宽, 并且在4 bit 位宽下…
面向神经形态系统的忆阻逻辑电路综述与展望
王佳阳， 董哲康， 纪晓悦， 胡小方… - 西南师范大学学报(自然 …, 2023 - xbgjxt.swu.edu.cn
… components such as diodes and transistors or integrated chips, … 3部分,本文介绍了忆阻逻辑
电路在神经形态系统中的应用现状;针对忆阻逻辑电路在操作复杂性和物理实现方面的缺陷,在第4…
电路在神经形态系统中的应用现状;针对忆阻逻辑电路在操作复杂性和物理实现方面的缺陷,在第4…