… , etc.), our goal is to create a programmable memory hierarchy all the way down to the
processor’s first level cache interface. Hence protocol controllers in our system have to sustain a …

Smart Memories Page 1 Abstract Trends in VLSI technology scaling demand that future
computing devices be narrowly focused to achieve high performance and high efficiency, yet …

… inside the HMC to support near memory computation in a modular and flexible fashion… smart
memory cube, and design a high bandwidth, low latency, and Advanced eXtensible Interface…

… Unlike these works, we focus on a context which external memory interface is not bandwidth
saturated and PIM’s benefits are determined only by latency. In addition, we utilize atomic …

… “Smart Memory Cube (SMC)”. SMC is build upon the existing HMC standard, and is compatible
with its interface, with no changes made to the memory … HMC IO interface specification, …

… for InMemory Computing architecture based on SRAM memory that embeds computing abilities.
This memory … To handle the interaction between the memory and the CPU, new memory …

… provides strong defenses against memory bus side channel remains elusive. This paper
observes that smart memory, memory with compute capability and a packetized interface, can …

… , the memory interface to the host … memory interface and memory-to-memory interconnect,
are specifically oriented towards architectures such as DIVA, in which PIMs are smart-memory …

… to the design of smart home interfaces for … memory is required as the user interface intelligence
level increases. Considering the evident decline in divided attention and working memory …

… smart interfaces that combine the functionality of the NCAP and STIM into a single sensor
interface… and STIM into an adaptable smart transducer interface and provide the most useful …