Statistical prediction of circuit aging under process variations

W Wang, V Reddy, B Yang… - 2008 IEEE Custom …, 2008 - ieeexplore.ieee.org
Accurate prediction of circuit aging and its variability is essential to reliable design and
analysis. Such a capability further helps reduce the load in statistical reliability test. Based
on compact models of transistor degradation and circuit performance, we develop analytical
solutions that efficiently predict the statistics of both circuit timing and the leakage under
temporal stress and process variations. These solutions prove that circuit aging and its
variance can be fully predicted from the characteristics of transistor degradation and circuit …

Statistical prediction of circuit aging under process variations

W Wang, V Reddy, V Balakrishnan… - Solid State Circuits …, 2010 - books.google.com
With relentless scaling of CMOS technology, circuit timing uncertainty due to temporal
degradation and static process variations poses a dramatic challenge to IC design
(International Technology Roadmap for Semiconductors, 2008; Reddy et al., 2002; Nassif,
2001; Lin et al., 1998). The deterioration of circuit performance over time, ie, aging, is usually
caused by several physical mechanisms such as channel-hot-carrier (CHC), negative-
biastemperature-instability (NBTI), and time-dependent-dielectric-breakdown …
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