A successive approximation resistor analog digital converter (SAR ADC) includes a first
conversion unit including a correction capacitor array and a bit capacitor array 2 V-1 less
than the number of a bit, a second conversion unit configured to differentially operate with
the first conversion unit, a comparator configured to output a voltage of a high level or a low
level of each capacitor according to output voltages of the first and second conversion units,
a successive approximation register (SAR) logic unit configured to receive an output voltage …

Abstract A SAR ADC converting an analog signal into a digital signal having N bits counting
from a most significant bit to a least significant bit includes a comparator comparing a
positive component with a negative component of the analog signal, two CDACs and a logic
circuit. For at least one i-th bit cycle of N bit cycle except a least significant bit cycle, one of a
pair of capacitors relating to (i+ 1)-th bit respectively arranged in the two CDACs is switched
according to a first comparing result of the comparator. After one of the pair of capacitors is …