The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a
discussion of power consumption that gives reasons for and consequences of increased
power during test. He ends with a discussion of the opportunity to use such techniques in
varying situations.

The System-On-Chip (SoC) revolution challenges both design and test engineers,
especially in the area of power dissipation. Generally, a circuit or system consumes more
power in test mode than in normal mode. This extra power consumption can give rise to
severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage.
Moreover, it can create problems such as increased product cost, difficulty in performance
verification, reduced autonomy of portable systems, and decrease of overall yield. Low …