Systolic architecture for integer point matrix multiplication using FPGA
DN Sonawane, MS Sutaone… - 2009 4th IEEE Conference …, 2009 - ieeexplore.ieee.org
DN Sonawane, MS Sutaone, I Malek
2009 4th IEEE Conference on Industrial Electronics and Applications, 2009•ieeexplore.ieee.org… Figure 2 shows proposed systolic architecture of four PE’s that have been used in realization
of matrix multiplication algorithm. … In this paper we presented resource efficient
implementation of integer point matrix multiplication algorithm that reduces the routing
complexity and improves the area/speed ratio. The proposed systolic architecture is generic and
can be implemented for any symmetric matrices using four PE’s for matrix sizes 4x4 and more.
We also claim that four PE’s are more efficient to have tradeoffs between area and execution …
of matrix multiplication algorithm. … In this paper we presented resource efficient
implementation of integer point matrix multiplication algorithm that reduces the routing
complexity and improves the area/speed ratio. The proposed systolic architecture is generic and
can be implemented for any symmetric matrices using four PE’s for matrix sizes 4x4 and more.
We also claim that four PE’s are more efficient to have tradeoffs between area and execution …
The paper presents a systolic architecture for integer point matrix multiplication algorithm using FPGA. Approach uses four processing elements that minimizes resources, reduces the routing complexity and improves Area/Speed metric.
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