The cipher consists of a 128-bit key and uses 8 rounds to encrypt a block of 64-bit data. It
makes use of the Feistel structure together with an S-Box and P-box. We implemented our
cipher on iNEXT-V6 test board, which is equipped with virtex6 FPGA. The design
synthesized to 196 slices at 337 MHz maximum clock frequency. The hardware results
indicate that our cipher uses minimal hardware resources and has greater throughput as …