Methods, storage mediums, and apparatuses for evaluating the reliability of Three-
Dimensional (3D) Network-on-Chip (NoC) designs are described. The described
embodiments provide a 3D NoC specific fault-injector tool which is able to model logic-level
fault models of 3D NoC specific physical faults in 3D-NoC platform. These embodiments
automate the whole process of static and dynamic fault injection base on the user
preference and reports the specific reliability metrics for 3D NoC platform as a single tool …

Technology scaling and higher operational frequencies are no longer sustainable at the
same pace as before. The processor industry is rapidly moving from a single core with high-
frequency designs to many-core with lower frequency chips; Network-on-Chip (NoC) has
been proposed as a scalable and efficient on-chip interconnection among cores. In addition,
employing Three-Dimensional (3D) integration instead of Two-Dimensional (2D) integration
is the other trend to keep the traditional expected performance improvements. The …