Response time of the dynamic back gate bias scaling of large scale digital modules implemented with silicon on thin BOX (SOTB) technology developed by LEAP was analyzed using real chips. A reconfigurable accelerator cool mega array (CMA) and two different prototypes of microcontroller V850 E-star were utilized for the measurement. Evaluation results revealed that the response time is related to the chip area which shares the bias voltage rather than the leakage current itself. The leakage current can be mostly stable 180.0 us and 270.2 us after changing bias voltage of CMA and V850E-Star, respectively. The possibility of the dynamic back gate bias scaling within milliseconds for dynamic reconfigurable architectures was shown.