Memristors are promising nanoelectronic devices for the implementation of future AI-driven sensor-processor electronic systems, which are essential for the ongoing digitalization of our world. Accurate and computationally cost-effective models for the manufactured memristors are essential for the design of such systems, especially for the simulation of large circuits. In this brief we address the simplification of the JART memristor model, a generic physics-based model of Valence Change Mechanism (VCM) memristors which accurately describes the dynamic behavior of fabricated memristor devices. Furthermore, the proposed model and simplification methodology have the potential to capture the dynamics of a wide range of memristor devices. Importantly, the implicit description of the current through the memristor is replaced by an explicit mathematical relationship. The proper reproduction of memristor dynamics, verified by applying the system-theoretic Dynamic Route Map (DRM) graphical analysis tool, applicable to first-order systems, can be observed through the proposed simplified model and enables the time-efficient simulation of large arrays of VCM devices.