We present the study of an analog hardware accelerator targeting the implementation of on-chip Neural Network (NN) inference for ADC-less and FPGA-less position sensitivity in Anger Cameras. We report high-level simulations based on MATLAB to emulate the operation of a 64-32-32-2 NN implemented in a CMOS process, exploring two reference studies: a PET detector and a SPECT detector, achieving a spatial resolution of 1.38 mm and 0.84 mm FWHM, respectively. The network parameters (weights, biases, and activation function) are then exploited in the design of a programmable, switched capacitor (SC)-based matrix for executing in charge domain the multiply-and-accumulate (MAC) operations needed for an inference step.