Transistor-level optimization of CMOS complex gates
VN Possani, FS Marques… - 2013 IEEE 4th Latin …, 2013 - ieeexplore.ieee.org
2013 IEEE 4th Latin American Symposium on Circuits and Systems …, 2013•ieeexplore.ieee.org
This paper presents a new methodology to generate efficient transistor networks. Transistor-
level optimization consists in an effective possibility to increase design quality when
generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input
ISOP, the proposed method is able to deliver series-parallel and non-series-parallel
arrangements with reduced transistor count. The experiments performed over the set of 4-
input P-class Booleans functions have demonstrated the efficiency of the proposed …
level optimization consists in an effective possibility to increase design quality when
generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input
ISOP, the proposed method is able to deliver series-parallel and non-series-parallel
arrangements with reduced transistor count. The experiments performed over the set of 4-
input P-class Booleans functions have demonstrated the efficiency of the proposed …
This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The experiments performed over the set of 4-input P-class Booleans functions have demonstrated the efficiency of the proposed approach.
ieeexplore.ieee.org
以上显示的是最相近的搜索结果。 查看全部搜索结果