… the recent advances in accelerator designs for deep neural networks (DNNs)—that is, DNN
… in accelerator designs for deep neural networks (DNNs)—that is, DNN accelerators. We …

… from the last 3 years of the hardware architectures research for DNNs. In this paper, the
reader will first understand what a hardware accelerator is, and what are its main components, …

… accelerator architectures for DNN acceleration. Section V shows a detailed review of GPU-based
accelerators for the acceleration … based accelerator architectures for DNN acceleration. …

… Overall Architecture We first describe an overall structure of the SNACC accelerator architecture.
SNACC is a multi-core accelerator with several cores each of which consists of a micro-…

… three major areas for improvements in the DNN architecture: Arithmetic logic unit, dataflow,
… of the ASIC accelerators for the DNN architectures. The state-of-the-art accelerators are …

… flexible interconnection, the DNN accelerator can support different … accelerator design.
This paper systematically investigates the interconnection networks in modern DNN accelerator …

Convolutional Neural Networks (CNN) are very computation-intensive. Recently, a lot of CNN
accelerators based on the CNN intrinsic parallelism are proposed. However, we observed …

… In this article, we demonstrate that FPGA acceleration can … accelerator architecture tailored
for bitwise convolution and normalization that features massive spatial parallelism with deep …

… Figure 5: Shown above is a high-level description of our accelerator architecture, results
from a DSE over the accelerator implementation space, and energy and area analysis of …

… In this section, we present the architecture of the hardware accelerator for running DCNNs
in the feedforward prediction phase. The capabilities and the limitations of this hardware were …