… and lower level cache designs that use STT-RAM. In particular, our designs use STTRAM
cells with … , made possible by different magnetic tunneling junction (MTJ) designs. For the fast …

… This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the
cache and memory system design by taking advantage of the opportunities brought by …

The on-chip memory is a dominant source of power and energy consumption in modern
and future processors. This paper explores the use of a new emerging non-volatile memory …

… We start by replacing all three levels of cache with the STT-RAM-based designs from
Section 3.4. The performance of this aggressive change is shown in Figure 13, with each bar …

… hybrid cache design for the APM technique has 16 STT-RAM … a 20 STT-RAM lines and 1
SRAM line hybrid cache with a … a 1MB SRAM cache bank and 2MB STT-RAM cache bank for a …

… the traditional STT-RAM dynamic nonuniform cache access (… and reduce 26.4% of STT-RAM
cache energy consumption, … of process variations on the STT-RAM design, we conducted …

… Moreover, we show that this design method can also reduce STT RAM cache energy … -speed
STT RAM cache design method that can improve the performance of STT RAM cache with …

… -RAM cells with lower retention time against the overhead for … cache lines with longer
lifetimes. In this paper, we compare 3 different STT-RAM based cache designs: (1) STTRAM cache …

… Targeting the L1 cache, due to its high number of dynamic operations, this paper aims to
mitigate the energy overheads of STT-RAM caches. We also aim to realize STT-RAM caches …

… rates, we utilize it to reduce write energy consumption of STT-RAM caches. • We propose
an STT-RAM last-level cache design that predicts and bypasses dead writes for write energy …