… This paper proposes a hardware efficient CNN accelerator that can execute different
convolution filters efficiently, such as 3 × 3, 4 × 4, 5 × 5, 3 × 3 stride 2, depthwise, and 1 × 1 …

… of an FPGA-based accelerator under given resources. Our main contributions are the
following: • We propose a parallel framework for FPGA-based CNN accelerators that exploits four …

… This work proposes an end-to-end FPGAbased CNN accelerator with all the layers mapped
on one chip so that different layers can work concurrently in a pipelined structure to increase …

… Edge TPUs are a domain of accelerators for low-power,edge … across 423K uniqueconvolutional
neural networks. Building upon … metrics ofEdge TPU accelerators. These learned models …

… hardware accelerators for convolutional neural networks (… mapped FPGA accelerator
architecture tailored for bitwise convolution and … A key advantage of the FPGA accelerator is that …

… reconfigurable accelerator for deep convolutional neural net… on eight-layer convolutional
neural network with leaky rectified … based on the convolution neural network with rank based …

… in convolutional neural network (CNN) models makes sparsity-aware CNN hardware designs
very attractive. The existing sparse CNN accelerators … sparse 2-D convolution, this paper …

… requirements for accelerators in various aspects. Precision-fixed accelerators lack the …
Kim, “BitBlade: Area and energyefficient precision-scalable neural network accelerator with …

… Plenty of existing accelerators are built for dense CNNs or … sparse accelerators on FPGAs,
the proposed accelerator can … Compared to prior dense accelerators, this accelerator can …

… in these neural network accelerators. Although we can extend CNN accelerators to run SpMMs
… accelerators since they are specialized for convolutions rather than matrix multiplications. …