… a loop retiming framework during compilation to reduce the migration overhead by changing
the interleaved memory access pattern. With the proposed loop retiming … of hybrid cache is …

… NVM-based hybrid cache while the migration-aware loop retiming approaches focusing on
… balanced loop retiming approach to effectively architect the STT-RAM-based hybrid cache for …

… -based hybrid cache while the migration-aware loop retiming … loop retiming to achieve a
comprehensive optimization considering ILP of ALUs and migration overhead of hybrid cache…

… loop retiming approach to reduce migrations in loops and thereby improve the energy efficiency
and performance of STTRAM based hybrid cache … very large in loops with intensive data …

… proposed—from intermediate fast memories (caches) to various prefetching and memory …
propose a new loop scheduling with memory management technique, Iterational Retiming with …

… data migration in hybrid SRAM/STT-MRAM caches. They also focus on hybrid main memory
… While all above studies mainly focus on the hybrid nature of specific cache levels, the scope …

… state-of-the-art cache simulators supporting different types (functional, timing), modes (trace…
for hybrid cache designs, HyCSim has built-in support for it. Every block has a loop block bit …

… Retiming Repetition (TRR) algorithm to combine the retiming … the execution time when
compared to results without retiming. … , we reduce loop execution time by retiming some nodes to …

… in the second-level cache generate a cache miss trap. Each … engine in software by a loop in
the trap handler which issues … system architectural simulator with a detailed timing model [3]. …

… For example, a while-loop will … hybrid methodology. For these tests, we have selected two
testbenches from the TACLeBench to perform timing measurements on their generated hybrid …