Adaptive placement and migration policy for an STT-RAM-based hybrid cache

Z Wang, DA Jiménez, C Xu, G Sun… - 2014 IEEE 20th …, 2014 - ieeexplore.ieee.org
… In the Sun-Hybrid technique, each cache set allocates 1 SRAM line. Thus we evaluate a
20 STT-RAM lines and 1 SRAM line hybrid cache with a 5.25MB capacity for Sun-Hybrid

Prediction hybrid cache: An energy-efficient STT-RAM cache architecture

J Ahn, S Yoo, K Choi - IEEE Transactions on Computers, 2015 - ieeexplore.ieee.org
hybrid caches, an STT-RAM based hybrid cache architecture with a novel block placement
policy. The key concept of it is write intensity prediction, which predicts write intensity of cache

STT-RAM based energy-efficiency hybrid cache for CMPs

J Li, CJ Xue, Y Xu - … IEEE/IFIP 19th International Conference on …, 2011 - ieeexplore.ieee.org
STT-RAM. In this paper, we propose to integrate STT-RAM with SRAM to construct a novel
hybrid cache … density of STT-RAM as well as smart cache management polices, the proposed …

Low power data-aware STT-RAM based hybrid cache architecture

M Imani, S Patil, T Rosing - 2016 17th international symposium …, 2016 - ieeexplore.ieee.org
… In this section we describe our proposed hybrid cache design with STT-RAM and SRAM
partitions. We design each partition differently based on the expected data distribution within it. …

Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems

Q Li, J Li, L Shi, M Zhao, CJ Xue… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
… part of hybrid cache. Furthermore… STT-RAMbased hybrid cache. Experimental results show
that, combining these two methods, on average, the number of write operations on STT-RAM

MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems

Q Li, J Li, L Shi, CJ Xue, Y He - Proceedings of the 2012 ACM/IEEE …, 2012 - dl.acm.org
Hybrid caches consisting of both STT-RAM and … hybrid cache, most work on hybrid caches
employs migration based strategies to dynamically move write-intensive data from STT-RAM

Prediction table based management policy for STT-RAM and SRAM hybrid cache

B Quan, T Zhang, T Chen, J Wu - 2012 7th International …, 2012 - ieeexplore.ieee.org
… to STT-RAM. The purpose of the hybrid cache design is to take advantage of both, STT-RAM
The hybrid cache is composed with a large STT-RAM and a small SRAM. The frequently-…

Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache

Q Li, M Zhao, CJ Xue, Y He - Proceedings of the 13th ACM SIGPLAN …, 2012 - dl.acm.org
… of the overhead of migrations in STT-RAM based hybrid caches. This paper focuses on
embedded systems, in which the configuration of only one-level cache is often applied, such as …

A novel STT-RAM-based hybrid cache for intermittently powered processors in IoT devices

M Xie, C Pan, Y Zhang, J Hu, Y Liu, CJ Xue - IEEE Micro, 2018 - ieeexplore.ieee.org
… Novel Hybrid Cache We design a novel hybrid one-level cache for intermittently powered …
In each cache set, there are both SRAM cache blocks and STT-RAM cache blocks. For the …

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

YT Chen, J Cong, H Huang, B Liu, C Liu… - … , Automation & Test …, 2012 - ieeexplore.ieee.org
hybrid cache architecture (RHC), in which NVM is incorporated in the last-level cache together
… Therefore, in this paper, we will focus on a hybrid cache architecture with STT-RAM as the …