… a very long instruction word (VLIW) processor design that ‘shares’ its cache blocks when
switching to … trigger cache resizing operations and improper use can lead to less efficient cache …

… cache misses of the VLIW core through the shared L2 cache, … potential of the proposed
hybrid multi-core architecture. … a hybrid dual-core processor, which is composed of a VLIW …

… processor performance by issuing multiple instructions from different threads. In VLIW processors,
… In this paper, we propose Hybrid MultiThreading (HMT), a technique that at each cycle …

… The loop retiming preliminaries as well as its applications for VLIW processors and STT-RAM-based
hybrid caches are introduced in Section 2. A motivational example is illustrated to …

… relative latency of such a centralized cache will increase, leading to an … cache among clusters
for clustered VLIW processors. We refer to this kind of design as fully distributed processors…

… as its applications for VLIW processors and STT-RAM-based hybrid caches are introduced …
on ILP of ALUs and on migration overhead in hybrid cache are studied in detail in Section 4. …

… cache with a zero miss rate, the CVLIW's performance is still 9%--15% higher than that of the
VLIW processor … The proposed CVLIW processor is a hybrid architecture that has inherited …

… Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that
on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor …

… impact of simultaneous instruction cache (I-cache) and issue-width reconfiguration for a very
long instruction word (VLIW) processor. The issue-width of the processor can be adjusted at …

… we present Hybrid-DBT, an open-source, hardware accelerated DBT system targeting VLIW
… memories: the translated binaries are written in the VLIW instruction cache and the profiling …