… For stencil loops with read and write data dependencies, we observe that migration … and
write memory access pattern in a memory block. This paper proposes a loop retiming framework …

… STT-RAM-based hybrid cache for VLIW processors. Addressing this issue, this paper
models … impacts of loop retiming on both ILP of ALUs and migration overhead in STT-RAM/SRAM …

… Unfortunately, the traditional ILP-aware loop retiming … -aware loop retiming approaches
focusing on memory part have not … loop retiming approach to effectively architect the STT-RAM-…

… data array operations in loops, migrations incline to be … a loop retiming approach to reduce
migrations in loops and thereby improve the energy efficiency and performance of STTRAM …

… Loops are usually the most computation intensive part of an embedded … for loop applications
on STT-RAM. A lot of work has been done to mitigate costly write operations on STT-RAM [4]…

… -RAM) as a new candidate for building caches [1]. Compared to SRAM, STTRAM has higher
storage density and negligible leakage … The kernel code is the loop starting at line 7. In this …

… TABLE I: The timing and energy parameters of 2/4/8MB STT-RAM LLC at 45nm technology
… eventually put the system into a negative feedback loop. The general solutions of this issue …

… 12(c), in the kth iteration of the outer loop, a special write … is amortized over all inner loop
iterations, and is observed to … operations to obtain array-level timing and energy characteristics. …

… Therefore, the combination of STT and TMR gives rise to the memory loops observed in
the … of the MTJ by proper timing of the pulse [45, 48, 49], in an analogous fashion to the C-…

… Recent advances in nonvolatile spin transfer torque (STT) RAM … We use the timing model in
[23] where the read access is 3 … The inner loop rotates N times. Then this process is repeated …