In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully
static operations is presented. The design is developed by using various circuit-reduction …

… Abstract— This paper enumerates low power, high speed design of flip-flop having less …
single phase clocking (TSPC) flip-flop. Compared to Conventional flipflop, it has 5 Transistors …

… This paper enumerates low power, high speed design of FlipFlops having less number of …
(TSPC) Flip-Flop. As transistors used have small area and low power consumption, they can …

… Unfortunately a correct timing of the flip-flop is guaranteed only if the gating logic is … low
power flip-flops will be presented. Proposed flip-flops use gating techniques to gain low power …

… flip-flop, ep-DCO, and the associated limitations. Section IV presents the new flip-flop utilizing
the new technique for low-power … and flip-flops for high-performance and low power system,…

… of power dissipation--of DET flip-flops over SET flip-flops-we are immediately forced to
consider which input vectors are to be used for the purposes of comparison. This is as power …

… flip-flops for low-energy systems with constant throughput. Characterization metrics, relevant
to low-… This methodology is applied to characterization of various flip-flop styles and their …

… low-power single-edge- and double-edge-triggered flipflops which were faster compared to
the previously proposed flip-flops … single-edge-triggered flip-flop (MHLFF) reduced the power …

In this paper, we propose a novel TFET Flip-Flop (TFET-FF) designed to address the requirements
of ULP (Ultra-Low-Power) applications, like IoT (Internet of Things), while maintaining …

In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved
using only 19 transistors is proposed. The design follows a master-slave-type logic structure …