… • Great redundancy in neural networks - VGG16 network can be compressed from 550MB to
11.3MB - FPGA has limited BRAM and DDR bandwidth … Deep Compression is useful in …

… hardware realization in the NIC. For seamless integration of the in-network accelerators
with the existing networking software … with the traditional TCP/IP network stack and Open-MPI …

… This paper presents a design methodology for accelerating CNNs using Hardware/Software
Co-design techniques, in order to balance performance and flexibility, particularly for …

… a software stack, we have made hybrid memristor-based ML accelerators more accessible
to software … network models developed using other frameworks to target these accelerators. …

… hardware accelerator cores such as pruning, quantization, or data reuse. In contrast, we
focus on the co-design approach to eventually resulting in system … hardware/software co-design …

… are useful to classify co-design problems. We consider next systemlevel co-design issues
for … units on a local area network), or lumped (eg, workstations). In this paper, we consider a …

… an efficient hardware/software co-design under the system … a hardware/software codesign
framework for a wireless sensor platform, which can adaptively change its hardware/software …

… we call “Dynamic Hardware/Software Co-Design”. The content … of-the-art of hardware/software
co-design, we discuss NoC-based … Dynamic Hardware/Software Co-Design is defined and …

… To use CMUL for deep neural network (DNN) acceleration, we propose a framework that
modifies the trained DNN model to make it suitable for approximate hardware. Our framework …

… 2020) leveraged multi-objective Bayesian optimization for neural network accelerator …
Co-design: There is a growing body of work exploring neural architecture search and hardware …