Performance evaluation of mesh-based NoCs: Implementation of a new architecture and routing algorithm

S Choudhary, S Qureshi - International Journal of Automation and …, 2012 - Springer
This paper presents the result of experiments conducted in mesh networks on different
routing algorithms, traffic generation schemes and switching schemes. A new network on …

[PDF][PDF] DMesh: a diagonally-linked mesh network-on-chip architecture

WH Hu, SE Lee, N Bagherzadeh - Network on Chip Architectures, 2008 - diit.unict.it
In this paper, we propose a new mesh-typed NoC architecture which aims at enhancing
network performance while keeping implementation cost feasible. The result is a diagonally …

[PDF][PDF] Evaluation of routing algorithms on mesh based nocs

AV de Mello, LC Ost, FG Moraes, NLV Calazans - PUCRS, Av. Ipiranga, 2004 - pucrs.br
The increasing complexity of integrated circuits drives the research of new on-chip
interconnection architectures. Networks-on-chip (NoCs) are a candidate architecture to be …

Traffic generation and performance evaluation for mesh-based NoCs

L Tedesco, A Mello, D Garibotti, N Calazans… - Proceedings of the 18th …, 2005 - dl.acm.org
The designer of a system on a chip (SoC) that connects IP cores through a network on chip
(NoC) needs methods to support application performance evaluation. Two key aspects …

FERONOC: flexible and extensible router implementation for diagonal mesh topology

M Elhajji, B Attia, A Zitouni, R Tourki… - Proceedings of the …, 2011 - ieeexplore.ieee.org
Networks on Chip (NoCs) can improve a set of performances criteria, in complex SoCs, such
as scalability, flexibility and adaptability. However, performances of a NoC are closely …

Low-latency multi-level mesh topology for NoCs

M Saneei, A Afzali-Kusha… - 2006 International …, 2006 - ieeexplore.ieee.org
In this paper, we introduce a new topology for network on chips which is named multi-level
mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this …

An adaptive congestion-aware routing algorithm for mesh network-on-chip platform

PT Huang, W Hwang - 2009 IEEE International SOC …, 2009 - ieeexplore.ieee.org
In this paper, an adaptive congestion-aware routing algorithm is proposed for mesh network-
on-chip (NoC) platforms. Depending on the traffic around the routed node, the proposed …

Star-type architecture with low transmission latency for a 2D mesh NOC

KJ Chen, CH Peng, F Lai - 2010 IEEE Asia Pacific Conference …, 2010 - ieeexplore.ieee.org
The 2D mesh network on chip (NOC) is a popular NOC topology because of network
scalability and the use of a simple routing algorithm. However, the long distance traffic may …

[PDF][PDF] Network on chip router for 2D mesh design

A Jain, A Kumar, R Dwivedi, S Sharma - International Journal of …, 2016 - academia.edu
The network version of the multiprocessor system on chip (MPSoC) is called Network on
Chip (NoC). The NoC approach has been proved one of the best techniques for the efficient …

Performance analysis of routing algorithms in mesh based network on chip using booksim simulator

W Myung, Z Qi, M Cheng - 2019 IEEE International Conference …, 2019 - ieeexplore.ieee.org
Network on Chip (NoC) that integrates a large number of nodes in a chip is a competitive
candidate to solve the problems of multi-core chip scalability and clock synchronization …