Implementing triple adjacent error correction in double error correction orthogonal Latin squares codes

P Reviriego, S Liu, JA Maestro, S Lee… - … on Defect and Fault …, 2013 - ieeexplore.ieee.org
Soft errors have been a concern in memories for many years. In older technologies, soft
errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets …

Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories

L Xiao, J Li, J Li, J Guo - Sixteenth international symposium on …, 2015 - ieeexplore.ieee.org
Soft errors have been a concern in memory reliability for many years. With device feature
size decreasing and memories density increasing, a single event upset (SEU) in memory …

Reducing the cost of triple adjacent error correction in double error correction orthogonal latin square codes

S Liu, P Reviriego, L Xiao… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a
growing interest on error correction codes that can correct multibit errors. Orthogonal Latin …

Concurrent error detection for orthogonal Latin squares encoders and syndrome computation

P Reviriego, S Pontarelli… - IEEE transactions on very …, 2012 - ieeexplore.ieee.org
Error correction codes (ECCs) are commonly used to protect memories against errors.
Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for …

Fault tolerant single error correction encoders

JA Maestro, P Reviriego, C Argyrides… - Journal of Electronic …, 2011 - Springer
Soft errors are an important issue for circuit reliability. To mitigate their effects on the system
functionality, different techniques are used. In many cases Error Correcting Codes (ECC) are …

Error detection and correction using decimal matrix code: Survey

TE Santhia, RHR Bharathi… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
Scaling of CMOS technology to nanoscale increases soft error rate in memory cells. Both
single bit upset and Multiple Cell Upsets (MCUs) causes reliability issues in memory …

Low delay error correction codes to correct stuck-at defects and soft errors

A Asuvaran, S Senthilkumar - 2014 International Conference …, 2014 - ieeexplore.ieee.org
For perfect communication during data transmission between transmitter and receiver the
reliability is important factor, sometimes reliability is missed due to appearance of errors …

Ultrafast single error correction codes for protecting processor registers

LJ Saiz-Adalid, P Gil, J Gracia-Morán… - 2015 11th European …, 2015 - ieeexplore.ieee.org
Error correction codes (ECCs) are commonly used in computer systems to protect
information from errors. For example, single error correction (SEC) codes are frequently …

Extend orthogonal Latin square codes for 32-bit data protection in memory applications

S Liu, L Xiao, Z Mao - Microelectronics Reliability, 2016 - Elsevier
As CMOS technology size scales down, multiple cell upsets (MCUs) caused by a single
radiation particle have become one of the most challenging reliability issues for memories …

Protection of on-chip memory systems against multiple cell upsets using double-adjacent error correction codes

H Jun, Y Lee - IEICE Transactions on Electronics, 2015 - search.ieice.org
As semiconductor devices scale into deep sub-micron regime, the reliability issue due to
radiation-induced soft errors increases in on-chip memory systems. Neutron-induced soft …