14.4 A Class F-1/F 24-to-31GHz power amplifier with 40.7% peak PAE, 15dBm OP1dB, and 50mW Psat in 0.13μm SiGe BiCMOS

SY Mortazavi, KJ Koh - 2014 IEEE International Solid-State …, 2014 - ieeexplore.ieee.org
The output power of power amplifiers (PAs) can be increased by using PA arrays and by
combining individual PA output powers either on chip with linear combiners or in free space …

A high-efficiency 142–182-GHz SiGe BiCMOS power amplifier with broadband slotline-based power combining technique

X Li, W Chen, S Li, Y Wang, F Huang… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
In this article, a high-efficiency broadband millimeter-wave (mm-Wave) integrated power
amplifier (PA) with a low-loss slotline-based power combing technique is proposed. The …

A D-band CMOS power amplifier for wireless chip-to-chip communications with 22.3 dB gain and 12.2 dBm P1dB in 65-nm CMOS technology

HS Son, CJ Lee, DM Kang, TH Jang… - 2018 IEEE Topical …, 2018 - ieeexplore.ieee.org
This paper presents a D-band linearized power amplifier (PA) with on-chip current
combining transformer using a standard 65nm CMOS process, which covers 114 to 131 …

High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOS

A Chakrabarti, H Krishnaswamy - Proceedings of the IEEE …, 2012 - ieeexplore.ieee.org
Stacking devices in CMOS power amplifiers (PAs) increases the achievable output voltage
swing, thereby increasing the output power and efficiency, particularly at millimeter-wave …

A 15 GHz-bandwidth 20dBm PSAT power amplifier with 22% PAE in 65nm CMOS

J Zhao, M Bassi, A Mazzanti… - 2015 IEEE Custom …, 2015 - ieeexplore.ieee.org
Generation of broadband power at mm-wave frequencies with high efficiency is challenging,
because of the low gain of CMOS devices and the trade-off between efficiency and gain …

24 GHz stacked power amplifier with optimum inter-stage matching using 0.13 μm CMOS process

J Chang, K Kim, S Lee, S Nam - 2011 3rd International Asia …, 2011 - ieeexplore.ieee.org
A single-stage 24 GHz triple stacked power amplifier using 0.13 μm CMOS process is
demonstrated. To Compare with parallel current combining method, series voltage …

2.4 GHz CMOS digitally programmable power amplifier for power back-off operation

F Santos, A Mariano, B Leite - 2016 IEEE 7th Latin American …, 2016 - ieeexplore.ieee.org
This paper presents the simulation results of a linear, fully integrated, two-stage digitally
programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is …

Optimized power combining technique to design a 20dB gain, 13.5 dBm OCP1 60GHz power amplifier using 65nm CMOS technology

S Aloui, Y Luque, N Demirel, B Leite… - 2012 IEEE Radio …, 2012 - ieeexplore.ieee.org
Millimeter-wave Distributed Active Transformer (DAT), baluns and zero degree 1-4 splitter
have been optimized to design a 60 GHz parallel Power Amplifier (PA). The implementation …

A 0.7–6GHz broadband CMOS power amplifier for multi-band applications

X Sun, F Huang, X Tang, M Shao - … International Conference on …, 2012 - ieeexplore.ieee.org
In this paper, a two-stage cascaded power amplifier (PA), which consists of cascode
topology, for Multi-band systems operating in the 0.7-6GHz frequency range is presented …

A 40-nm CMOS E-band 4-way power amplifier with neutralized bootstrapped cascode amplifier and optimum passive circuits

D Zhao, P Reynaert - IEEE Transactions on Microwave Theory …, 2015 - ieeexplore.ieee.org
This paper reports a fully integrated 40-nm CMOS power amplifier (PA) for E-band
applications. A neutralized bootstrapped cascode amplifier (NBCA) topology is proposed to …