A mess of memory system benchmarking, simulation and application profiling

P Esmaili-Dokht, F Sgherzi, VS Girelli… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
The Memory stress (Mess) framework provides a unified view of the memory system
benchmarking, simulation and application profiling. The Mess benchmark provides a holistic …

Anatomy: An analytical model of memory system performance

N Gulur, M Mehendale, R Manikantan… - ACM SIGMETRICS …, 2014 - dl.acm.org
Memory system design is increasingly influencing modern multi-core architectures from both
performance and power perspectives. However predicting the performance of memory …

PROFET: Modeling system performance and energy without simulating the CPU

M Radulovic, R Sánchez Verdejo, P Carpenter… - Proceedings of the …, 2019 - dl.acm.org
The approaching end of DRAM scaling and expansion of emerging memory technologies is
motivating a lot of research in future memory systems. Novel memory systems are typically …

Characterizing emerging heterogeneous memory

D Shen, X Liu, FX Lin - ACM SIGPLAN Notices, 2016 - dl.acm.org
Heterogeneous memory (HM, also known as hybrid memory) has become popular in
emerging parallel architectures due to its programming flexibility and energy efficiency …

Dramsim: a memory system simulator

D Wang, B Ganesh, N Tuaycharoen, K Baynes… - ACM SIGARCH …, 2005 - dl.acm.org
As memory accesses become slower with respect to the processor and consume more
power with increasing memory size, the focus of memory performance and power …

Membrain: Automated application guidance for hybrid memory systems

MB Olson, T Zhou, MR Jantz, KA Doshi… - … and Storage (NAS), 2018 - ieeexplore.ieee.org
Computer systems with multiple tiers of memory devices with different latency, bandwidth,
and capacity characteristics are quickly becoming mainstream. Due to cost and physical …

Dram bandwidth and latency stacks: Visualizing dram bottlenecks

S Eyerman, W Heirman, I Hur - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
For memory-bound applications, memory bandwidth utilization and memory access latency
determine performance. DRAM specifications mention the maximum peak bandwidth and …

A scalable analytical memory model for CPU performance prediction

G Chennupati, N Santhi, R Bird, S Thulasidasan… - … , and Simulation: 8th …, 2018 - Springer
As the US Department of Energy (DOE) invests in exascale computing, performance
modeling of physics codes on CPUs remain a challenge in computational co-design due to …

PIMSys: A Virtual Prototype for Processing in Memory

D Christ, L Steiner, M Jung, N Wehn - Proceedings of the International …, 2024 - dl.acm.org
Data-driven applications are increasingly central to our information technology society,
propelled by AI techniques reshaping various sectors of our economy. Despite their …

Bandwidth Limits in the Intel Xeon Max (Sapphire Rapids with HBM) Processors

JD McCalpin - International Conference on High Performance …, 2023 - Springer
The HBM memory of Intel Xeon Max processors provides significantly higher sustained
memory bandwidth than their DDR5 memory, with corresponding increases in the …