Semiconductor devices having electrically and optically conductive vias, and associated systems and methods

E Nakano, ME Tuttle - US Patent 10,141,259, 2018 - Google Patents
Semiconductor devices having one or more vias filled with a transparent and electrically
conductive material are disclosed herein. In one embodiment, a semiconductor device …

Multi-chip flip package with substrate for inter-die coupling

L Swanson, W Boyd - US Patent App. 10/827,836, 2005 - Google Patents
BACKGROUND 0001 Advances in integrated circuit (“IC) packaging techniques allow
designers to fabricate IC packages that continue to decrease in size and increase in power …

Forming and/or configuring stacked dies

P Jain, M Voogel, B Gaide - US Patent 11,043,480, 2021 - Google Patents
Examples described herein generally relate to forming and/or configuring a die stack in a
multi-chip device. An example is a method of forming a multi-chip device. Dies are formed …

Substrate Dicing

JC Lin, CW Wu, SW Lu, S Jeng… - US Patent App. 13/216,825, 2013 - Google Patents
(57) ABSTRACT A method and apparatus for separating a substrate into indi vidual dies and
the resulting structure is provided. A modifi cation layer, such as an amorphous layer, is …

Stacked semiconductor die assemblies with partitioned logic and associated systems and methods

J Li, SK Groothuis - US Patent App. 14/242,485, 2015 - Google Patents
BACKGROUND 0002 Packaged semiconductor dies, including memory chips,
microprocessor chips, and imager chips, typically include a semiconductor die mounted on a …

Packages with thermal management features for reduced thermal crosstalk and methods of forming same

KH Chen, W Hung, SP Huang, S Jeng - US Patent 9,269,694, 2016 - Google Patents
BACKGROUND In the packaging of integrated circuits, semiconductor dies may be stacked
through bonding, and may be bonded to other package components such as interposers …

Backside illuminated image sensors with stacked dies

S Borthakur, S Churchwell, U Boettiger… - US Patent …, 2015 - Google Patents
BACKGROUND The present invention relates to imaging devices, and, more particularly, to
image sensor units formed using stacked image sensor and processor integrated circuits …

Low-cost flip-chip interconnect with an integrated wafer-applied photo-sensitive adhesive and metal-loaded epoxy paste system

RC Dunne, MW Cowens, MA Bolanos - US Patent App. 12/642,445, 2010 - Google Patents
Various exemplary embodiments provide materials and methods for flip-chip packaging
technology. The disclosed flip-chip packaging technology can use a single B-stage wafer …

Curved heat spreader design for electronic assemblies

D Lu, W Shi - US Patent App. 11/618,263, 2008 - Google Patents
0001 Integrated circuits may beformed on semiconductor wafers that are formed from
materials such as silicon. The semiconductor wafers are processed to form various elec …

Interconnect structures with polymer core

S Razdan, ER Prack, S Agraharam… - US Patent …, 2015 - Google Patents
BACKGROUND First-level interconnect (FLI) structures may include bulk solder interconnect
structures to couple a die with another component (eg, another die or Substrate) of an …