Decision feedback equalization (DFE) circuitry and method for equalizing data signals over
a wide range of data rates. By using delayed and controlled versions of the recovered data …

(57) ABSTRACT A Decision Feedback Equalizer (DFE) with programmable taps includes a
Summer configured to receive a DFE input signal. Delay elements are coupled to the …

In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as
those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing …

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to
receive serial data, at an analog input, at a first data rate. The two-stage decision feedback …

Disclosed are a receiver circuit, method and design architec ture of a decision feedback
equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one …

(57) ABSTRACT A decision feedback equalizer includes a correction circuit to correct a
sampled value of an incoming bit based on interSym bol interference of at least one …

(57) ABSTRACT A decision feedback equalizer includes a correction circuit to correct a
sampled value of an incoming bit based on interSym bol interference of at least one …

FEEDBACK EQUALIZER A digital transmission is susceptible to impairments resulting in
degradation of signal quality. Receivers for digital communications must be capable of …

Methods and apparatus are provided for generating one or more clock signals for a decision-
feedback equalizer using DFE detected data. A received signal is sampled using a data …

Appl. No.: 11/299,975 A method and apparatus for advantageously utilizing the reset (22)
Filed: Dec. 12, 2005 state of an RTZ shift register to guarantee proper data align ment at the …