An improved contactless EPROM array, EPROM cell design, and method for fabricating the
same is based on a unique drain-source-drain configuration, in which a single source …

PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS
floating gate transistor com prises a floating gate and a gate oxide layer between the floating …

(57) ABSTRACT A nonvolatile memory cell is constructed using a? oating gate (FG) pFET
Readout Transistor (RT) having its source tied to a poWer source (Vdd) and its drain …

A non-volatile memory device is fabricated having enhanced charge retention capability.
Enhanced charge retention is achieved upon the floating gate of the non-volatile memory …

BACKGROUND OF THE INVENTION Electrically-programmable, read-only memories
(EPROMs) and electrically-programmable, electrically erasable read-only memories …

In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed
before the floating gates. In some embodiments, the memory cell also has control gates …

57 ABSTRACT A cross point EPROM array has trenches to provide improved isolation
between adjacent buried N--bit lines at locations where the adjacent buried N--bitlines are …

In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (eg
polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made …

The memory cell is formed in a body of a P-type semicon ductor material forming a channel
region and housing N-type drain and source regions at tWo opposite sides of the channel …

Non-volatile memory transistors are provided that include a floating gate formed from first
and Second layers of material Such as polysilicon. The Second floating gate layer is selec …