Analog-to-digital converter-based serial links: An overview
The ever-increasing number of networked devices and cloud computing applications has
created dramatic growth in data center traffic. This necessitates that the serial links that …
created dramatic growth in data center traffic. This necessitates that the serial links that …
22.4 A 32Gb/s digital-intensive single-ended PAM-4 transceiver for high-speed memory interfaces featuring a 2-tap time-based decision feedback equalizer and an in …
Single-ended transceivers that can deliver high-data rates at reduced supply voltages are
required to meet the ever-growing demands of future memory interfaces. The performance of …
required to meet the ever-growing demands of future memory interfaces. The performance of …
Digital equalization with ADC-based receivers: Two important roles played by digital signal processingin designing analog-to-digital-converter-based wireline …
Wireline input/output (I/O) bandwidth demand within networks in large data centers has
increased rapidly over the last decade because of the explosion in data generation from …
increased rapidly over the last decade because of the explosion in data generation from …
An 182mW 1-60Gb/s configurable PAM-4/NRZ transceiver for large scale ASIC integration in 7nm FinFET technology
N Kocaman, U Singh, B Raghavan… - … Solid-State Circuits …, 2022 - ieeexplore.ieee.org
With the COVID–19 pandemic, the faster and more reliable connectivity solutions in data
centers became the critical enabler technology of our daily activities. The current 50G data …
centers became the critical enabler technology of our daily activities. The current 50G data …
[图书][B] System-driven circuit design for ADC-based wireline data links
K Zheng - 2018 - search.proquest.com
In the era of connectivity, wireline I/O has been a key technology underpinning the
aggressive performance improvements of computer and communication systems. All …
aggressive performance improvements of computer and communication systems. All …
Design space exploration of single-lane OFDM-based serial links for high-speed wireline communications
G Kim - IEEE Open Journal of Circuits and Systems, 2022 - ieeexplore.ieee.org
The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-
based receiver (RX) has become the most commonly employed modulation for ultra-high …
based receiver (RX) has become the most commonly employed modulation for ultra-high …
3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS
K Gopalakrishnan, A Ren, A Tan… - … Solid-State Circuits …, 2016 - ieeexplore.ieee.org
High-speed signaling using NRZ has approached speeds above 50Gb/s where it is
extremely difficult to maintain power efficiency and performance over a wide variety of …
extremely difficult to maintain power efficiency and performance over a wide variety of …
11.8 An echo-cancelling front-end for 112Gb/s PAM-4 simultaneous bidirectional signaling in 14nm CMOS
R Farjadrad, K Kaviani, D Nguyen… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
The rapid growth of hyperscale data centers has led to an increased demand for high-speed
and low-latency data connectivity solution upgrades, which are power-efficient and minimal …
and low-latency data connectivity solution upgrades, which are power-efficient and minimal …
8.7 A 112Gb/s ADC-DSP-based PAM-4 transceiver for long-reach applications with> 40dB channel loss in 7nm FinFET
Driven by the proliferation of rich media services and a drastic increase of data availability,
the demand for high-speed data transfer in the data center continues to grow at greater than …
the demand for high-speed data transfer in the data center continues to grow at greater than …
A maximum-likelihood sequence detection powered ADC-based serial link
A 0.88 mm 2 65-nm analog-to-digital converter (ADC)-based serial link transceiver is
designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The …
designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The …