We describe a novel design for low-density parity-check (LDPC) codes that eliminates the
routing problem associated with LDPC decoder implementation resulting in a small silicon …

We present several hardware architectures to implement low-density parity-check (LDPC)
decoders for codes constructed with a hierarchical structure. The proposed hierarchical …

A novel parity-check matrix design for low-density parity-check (LDPC) codes is described.
By eliminating the routing problem associated with LDPC codes, the design results in a …

In this paper, we present a new, hardware-oriented technique for designing Low Density
Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient …

This paper presents a construction for low and high rate Low-Density Parity Check (LDPC)
codes, their performance and efficient hardware implementation. The problem with decoding …

Low-density parity-check (LDPC) codes have been shown to have good error correcting
performance approaching Shannon's limit. Good error correcting performance enables …

Low-density parity-check (LDPC) code, a very promising near-optimal error correction code
(ECC), is being widely considered in next generation industry standards. The VLSI …

This paper presents a system architecture for low-density parity-check (LDPC) codes that
allows dynamic switching of LDPC codes within the encoder and decoder without hardware …

We have designed and implemented the LDPC decoder chip with memory-reduction
method to achieve high-throughput and practical chip size. The decoder decodes (3, 6) …

Recently, low-density parity-check (LDPC) codes have attracted much attention because of
their excellent error-correcting performance and highly parallelizable decoding scheme …