3D-stacked memory architectures for multi-core processors

GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …

Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy

GH Loh - Proceedings of the 42nd Annual IEEE/ACM …, 2009 - dl.acm.org
3D-integration is a promising technology to help combat the" Memory Wall" in future multi-
core processors. Past work has considered using 3D-stacked DRAM as a large last-level …

Simultaneous multi-layer access: Improving 3D-stacked memory bandwidth at low cost

D Lee, S Ghose, G Pekhimenko, S Khan… - ACM Transactions on …, 2016 - dl.acm.org
3D-stacked DRAM alleviates the limited memory bandwidth bottleneck that exists in modern
systems by leveraging through silicon vias (TSVs) to deliver higher external memory …

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth

DH Woo, NH Seong, DL Lewis… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
Memory bandwidth has become a major performance bottleneck as more and more cores
are integrated onto a single die, demanding more and more data from the system memory …

Mitigating memory wall effects in high-clock-rate and multicore CMOS 3-D processor memory stacks

P Jacob, A Zia, O Erdogan, PM Belemjian… - Proceedings of the …, 2009 - ieeexplore.ieee.org
Three-dimensional chip (3-D) stacking technology provides a new approach to address the
so-called memory wall problem. Memory processor chip stacking reduces this memory wall …

Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints

J Meng, K Kawakami, AK Coskun - Proceedings of the 49th Annual …, 2012 - dl.acm.org
3D multicore systems with stacked DRAM have the potential to boost system performance
significantly; however, this performance increase may cause 3D systems to exceed the …

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

AK Mishra, X Dong, G Sun, Y Xie… - ACM SIGARCH …, 2011 - dl.acm.org
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being
explored as potential replacements to existing on-chip caches or main memories for future …

Enabling practical processing in and near memory for data-intensive computing

O Mutlu, S Ghose, J Gómez-Luna… - Proceedings of the 56th …, 2019 - dl.acm.org
Modern computing systems suffer from the dichotomy between computation on one side,
which is performed only in the processor (and accelerators), and data storage/movement on …

ATCache: Reducing DRAM cache latency via a small SRAM tag cache

CC Huang, V Nagarajan - … of the 23rd international conference on …, 2014 - dl.acm.org
3D-stacking technology has enabled the option of embedding a large DRAM onto the
processor. Prior works have proposed to use this as a DRAM cache. Because of its large …

Processing data where it makes sense: Enabling in-memory computation

O Mutlu, S Ghose, J Gómez-Luna… - Microprocessors and …, 2019 - Elsevier
Today's systems are overwhelmingly designed to move data to computation. This design
choice goes directly against at least three key trends in systems that cause performance …