Reconfigurable coprocessors synthesis in the MPEG-RVC domain

C Sau, L Fanni, P Meloni, L Raffo… - … Computing and FPGAs …, 2015 - ieeexplore.ieee.org
Flexibility and high efficiency are common design drivers in the embedded systems domain.
Coarse-grained reconfigurable coprocessors can tackle these issues, but they suffer of …

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

C Sau, L Raffo, F Palumbo, E Bezati… - 2014 International …, 2014 - ieeexplore.ieee.org
Specialized hardware infrastructures for efficient multi-application runtime reconfigurable
platforms require to address several issues. The higher is the system complexity, the more …

A prototyping environment for high performance reconfigurable computing

G Afonso, JL Dekeyser, RB Atitallah… - … -centric Systems-on …, 2011 - ieeexplore.ieee.org
In the face of power wall and high performance requirements, designers of hardware
architectures are directed more and more towards reconfigurable computing with the usage …

MARC: A many-core approach to reconfigurable computing

I Lebedev, S Cheng, A Doupnik, J Martin… - 2010 international …, 2010 - ieeexplore.ieee.org
We present a Many-core Approach to Reconfigurable Computing (MARC), enabling efficient
high-performance computing for applications expressed using parallel programming models …

Design of a flexible coprocessor unit

T Harbaum, D Meier, M Prinke… - … . Informatics: Theory and …, 1999 - ieeexplore.ieee.org
Todays FPGA technology allows reconfigurable hardware to be integrated into standard PC
hardware. A hardware like this allows for on-the-fly reconfigurable hardware. It is possible to …

Hardware/software design space exploration for a reconfigurable processor

A La Rosa, L Lavagno… - 2003 Design, Automation …, 2003 - ieeexplore.ieee.org
This paper describes an approach to hardware/software design space exploration for
reconfigurable processors. The existing compiler tool-chain, because of the user-definable …

Partial online-synthesis for mixed-grained reconfigurable architectures

A Grudnitsky, L Bauer, J Henkel - 2012 Design, Automation & …, 2012 - ieeexplore.ieee.org
Processor architectures with Fine-Grained Reconfigurable Accelerators (FGRAs) allow for a
high degree of adaptivity to address varying application requirements. When processing …

Compression based efficient and agile configuration mechanism for coarse grained reconfigurable architectures

SMAH Jafri, A Hemani, K Paul, J Plosila… - … on Parallel and …, 2011 - ieeexplore.ieee.org
This paper considers the possibility of speeding up the configuration by reducing the size of
configware in coarse grained reconfigurable architectures (CGRAs). Our goal was to reduce …

A reconfigurable processor architecture combining multi-core and reconfigurable processing unit

L Yan, B Wu, Y Wen, S Zhang… - 2010 10th IEEE …, 2010 - ieeexplore.ieee.org
It's a promising way to improve performance significantly by adding reconfigurable
processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core …

CREC: a novel reconfigurable computing design methodology

O Cret, K Pusztai, C Vancea… - … International Parallel and …, 2003 - ieeexplore.ieee.org
The main research done in the field of reconfigurable computing was oriented towards
applications involving low granularity operations and high intrinsic parallelism. CREC is an …