R Jayagowri, KS Gurumurthy - Progress in VLSI Design and Test: 16th …, 2012 - Springer
We present a technique to reduce the power of combinational circuits during testing. Power dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …
M Vidhyia, K Paramasivam, S Elayaraja… - Asian Journal of …, 2015 - ajesjournal.org
Power consumption is one of the biggest challenges in high performance VLSI design and testing. Low power VLSI circuits dissipate more power during testing when compared with …
AM Sudha - Proc Int J Electr Energy, 2014 - ijoee.org
Power consumption is one of the biggest challenges in high performance VLSI design and testing. Low power VLSI circuits dissipate more power during testing when compared with …
R Jayagowri, KS Gurumurthy - 2012 International Conference …, 2012 - ieeexplore.ieee.org
Power consumption of a circuit is more in test mode than normal mode. The increased heat due to excess power dissipation can open up reliability issue due to electro-migration. In …
Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test (CUT). In this paper we present a novel method …
Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power …
Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power …
B Singh, SB Narang, A Khosla - Acta Technica Napocensis, 2012 - users.utcluj.ro
Power optimization is one of the important challenges in VLSI circuit for testing engineers. Larger power dissipation becomes the reason for overheating and with every increase in …
Power dissipation during testing of VLSI circuits is major concern due to the switching activity of the circuit under test. In this paper, a novel method is presented, that aims at …