SUMMARY A single-poly memory cell is disclosed herein which overcomes problems in the
art described above. In accor dance with the present invention, a P-channel single-poly flash …

SUMMARY A Single-poly memory cell is disclosed herein which overcomes problems in the
art described above. In accor dance with the present invention, a P-channel Single-poly …

A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin
runnel oxide is provided between the well surface and an overlying floating gate. In one …

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to
semiconductor memories and more particularly to flash EEPROM cells and the method of …

57 ABSTRACT AP-channel flash EEPROM cell has P. source and P--drain regions, and a
channel extending therebetween, formed in an N-type well. Athin layer of tunnel oxide is …

57 ABSTRACT A method of semiconductor fabrication, in which a single aperture is used to
define both a thin oxide tunnel ing region and a drain diffusion region in a self-aligned …

A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions
and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon …

Accordingly, exemplary embodiments of the present invention are directed to single poly
flash EEPROM cells which avoid the drawbacks of conventional two poly stacked gate cells …

A memory array (10) is provided with a plurality of Flash EEPROM memory cells (24) that are
fabricated with a single level poly process. Each of the transistor cells (24) is fabricated from …

A new method of fabricating and programming and erasing a Flash EEPROM memory cell is
achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying …