Reducing bypass‐based network‐on‐chip latency using priority mechanism

AF Noghondar, M Reshadi… - IET Computers & Digital …, 2018 - Wiley Online Library
In the movement from a multi‐core to a many‐core era, cores count on the chip increases
quickly thus interconnect plays a large role in achieving the desired performance. Network …

A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison

K Gaffour, MK Benhaoua, AH Benyamina… - International Journal of …, 2023 - Taylor & Francis
Network on-Chip (NoC) is scalable, flexible, modular communication structure for Multi/Many-
core architectures. It allows simpler interconnect models with higher bandwidth compared to …

A low-cost and latency bypass channel-based on-chip network

A Fadakar Noghondar, M Reshadi - The Journal of Supercomputing, 2015 - Springer
The number of cores on the chip increases rapidly; therefore, scalability is the most
important design choice. Mesh-based Networks-on-Chip (NoC) are the most widely used …

Local congestion avoidance in network-on-chip

M Tang, X Lin, M Palesi - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
Network-on-Chip (NoC) has been made the communication infrastructure for many-core
architecture. NoC are subject to congestion, which is claimed to be avoided by many …

Area and power-efficient innovative congestion-aware Network-on-Chip architecture

C Wang, WH Hu, SE Lee, N Bagherzadeh - Journal of Systems …, 2011 - Elsevier
This paper proposes a novel Network-on-Chip architecture that not only enhances network
transmission performance while maintaining a feasible implementation cost, but also …

Review, analysis, and implementation of path selection strategies for 2D NoCS

R Singh, MK Bohra, P Hemrajani, A Kalla… - IEEE …, 2022 - ieeexplore.ieee.org
Recent advances in very-large-scale integration (VLSI) technologies have offered the
capability of integrating thousands of processing elements onto a single silicon microchip …

Design and implementation of congestion aware router for network-on-chip

MT Balakrishnan, TG Venkatesh, AV Bhaskar - Integration, 2023 - Elsevier
Abstract Network-on-Chip (NoC) is the state of the art on-chip interconnection network for
packet based communication. NoCs can offer low packet latency, high bandwidth, high …

Runtime buffer management to improve the performance in irregular Network-on-Chip architecture

RP PERINBAM J - Sadhana, 2015 - Springer
This paper presents a heterogeneous adaptable router to reduce latency in irregular mesh
Network-on-Chip (NoC) architectures. Regular mesh-based NoC architecture may become …

Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines

D Deb, J Jose, S Das, HK Kapoor - Journal of Parallel and Distributed …, 2019 - Elsevier
Advancements in CMOS technology led to the increase in number of processing cores on a
single chip. Communication between different cores in such multicore systems is facilitated …

[PDF][PDF] Power & Area Efficient Router in 2-D Mesh Network-on-Chip Using Low Power Methodology-Clock Gating Techniques

JD Principal - International Journal of Hybrid Information …, 2012 - researchgate.net
Abstract Network-on-Chip (NoC) is the interconnection platform that answers the
requirements of the modern on-Chip design. Small optimizations in NoC router architecture …