Heterogeneous processor architecture for integrating CNN and RNN into single high-performance, low-power chip

D Shin, J Lee, J Lee, JH Lee - US Patent 11,263,515, 2022 - Google Patents
A heterogeneous processor architecture for integrating a convolutional neural network
(CNN) and a recurrent neural network (RNN) into a single high-performance, low-power …

Processor with hybrid coprocessor/execution unit neural network unit

GG Henry, T Parks - US Patent 10,585,848, 2020 - Google Patents
(57) ABSTRACT A processor includes a front-end portion that issues instruc-tions to
execution units that execute the issued instructions. A hardware neural network unit (NNU) …

Neural network processor with direct memory access and hardware acceleration circuits

JR Goulding, JE Mixter, DR Mucha - US Patent 10,872,290, 2020 - Google Patents
(57) ABSTRACT A dynamically adaptive neural network processing system includes
memory to store instructions representing a neural network in contiguous blocks, hardware …

Neural network processor using compression and decompression of activation data to reduce memory bandwidth utilization

JL Corkery, BE Lundell, LM Wall, CB McBRIDE… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A deep neural network (“DNN”) module compresses and decompresses
neuron-generated activation data to reduce the utilization of memory bus bandwidth. The …

Neural network processor incorporating multi-level hierarchical aggregated computing and memory elements

A Baum, O Danon, H Zeitlin, D Ciubotariu… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A novel and useful neural network (NN) processing core adapted to
implement artificial neural networks (ANNs). The NN processor is constructed from self …

Neural network architecture using convolution engine filter weight buffers

C Martin - US Patent 11,182,668, 2021 - Google Patents
Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the
hardware comprising a plurality of convolution engines each configured to perform …

Vector computation unit in a neural network processor

GM Thorson, CA Clark, D Luu - US Patent 10,074,051, 2018 - Google Patents
A circuit for performing neural network computations for a neural network comprising a
plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of …

Neural network processor incorporating inter-device connectivity

A Baum, O Danon, H Zeitlin, D Ciubotariu… - US Patent …, 2023 - Google Patents
US11675693B2 - Neural network processor incorporating inter-device connectivity - Google
Patents US11675693B2 - Neural network processor incorporating inter-device connectivity …

Neural network processor

J Ross, NP Jouppi, AE Phelps, RC Young… - US Patent …, 2017 - Google Patents
A circuit for performing neural network computations for a neural network comprising a
plurality of neural network layers, the circuit comprising: a matrix computation unit configured …

Layer-based operations scheduling to optimise memory for CNN applications

JA Ambrose, I Ahmed, Y Yachide, H Bokhari… - US Patent …, 2020 - Google Patents
A method of configuring a System-on-Chip (SoC) to execute a Convolutional Neural
Network (CNN) by (i) receiving scheduling schemes each specifying a sequence of …