Arithmetic for high speed FFT implementation
EE Swartzlander, J Eldon - 1985 IEEE 7th Symposium on …, 1985 - ieeexplore.ieee.org
This paper describes recent progress in the implementation of high speed spectrum analysis
systems with state-of-the-art commercial and semi-custom VLSI circuits. Initial efforts are …
systems with state-of-the-art commercial and semi-custom VLSI circuits. Initial efforts are …
An ultra-high speed FFT processor
R Collesidis, T Dutton, J Fisher - ICASSP'80. IEEE International …, 1980 - ieeexplore.ieee.org
Modern high-speed programmable digital signal processors and array processors have
made possible real-time spectrum analysis using the Fast Fourier Transform algorithm on …
made possible real-time spectrum analysis using the Fast Fourier Transform algorithm on …
VHDL core for 1024-point radix-4 FFT computation
JA Vite-Frias, RJ Romero-Troncoso… - 2005 International …, 2005 - ieeexplore.ieee.org
This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications
in hardware signal processing, targeting low-cost FPGA technologies. The developed core …
in hardware signal processing, targeting low-cost FPGA technologies. The developed core …
FFT Implementation on the TMS320C30
PE Papamichalis - … Conference on Acoustics, Speech, and Signal …, 1988 - computer.org
The implementation of several FFT (fast Fourier transform) algorithms on the TMS320C30,
the third-generation device in the Texas Instruments family of digital signal processors is …
the third-generation device in the Texas Instruments family of digital signal processors is …
A radix-12 FFT building block
SA White - Proceedings of 27th Asilomar Conference on …, 1993 - ieeexplore.ieee.org
By increasing the radix of an FFT building block, we can reduce the total number of
arithmetic operations required to perform short-term spectral analyses. For a number of …
arithmetic operations required to perform short-term spectral analyses. For a number of …
A pipeline architecture for modified higher radix FFT
E Bernard, JG Krammer, M Sauer… - … ] ICASSP-92: 1992 …, 1992 - ieeexplore.ieee.org
A method, called twiddle-factor-shift, which combines the simplicity of interconnections and
processor elements (PEs) of radix-2 fast Fourier transform (FFT) algorithms and of the lower …
processor elements (PEs) of radix-2 fast Fourier transform (FFT) algorithms and of the lower …
Fast transform processor implementation
E Swartzlander, G Hallnor - ICASSP'84. IEEE International …, 1984 - ieeexplore.ieee.org
This paper describes recent progress in implementation of a 40 MHz (complex) data rate
frequency domain adaptive digital filter. The filter uses multiple time overlapped channels …
frequency domain adaptive digital filter. The filter uses multiple time overlapped channels …
High speed FFT processor implementation
EE Swartzlander, ZZ Stroll - MILCOM 1984-IEEE Military …, 1984 - ieeexplore.ieee.org
This paper describes recent progress in the implementation of a high speed Fast Fourier
Transform (FFT) processor with state-of-the-art VLSI circuits. Initial efforts have produced …
Transform (FFT) processor with state-of-the-art VLSI circuits. Initial efforts have produced …
Benchmarking of FFT algorithms
M Balducci, A Ganapathiraju, J Hamaker… - … '97.'Engineering the …, 1997 - ieeexplore.ieee.org
A large number of fast Fourier transform (FFT) algorithms have been developed over the
years. Among these, the most promising are the radix-2, radix-4, split-radix, fast Hartley …
years. Among these, the most promising are the radix-2, radix-4, split-radix, fast Hartley …
Application-specific DSP architecture for fast Fourier transform
KL Heo, SM Cho, JH Lee… - … on Application-Specific …, 2003 - ieeexplore.ieee.org
We present ASDSP (application-specific digital signal processor) instructions and their
hardware architecture for high-speed FFT. The proposed instructions calculate a butterfly …
hardware architecture for high-speed FFT. The proposed instructions calculate a butterfly …