VLSI implementation of low power scan based testing
S Ukey, S Rathkanthiwar… - … on Communication and …, 2016 - ieeexplore.ieee.org
Power consumption in test becomes a higher barrier for consideration in test of any
combinational circuit is high during test mode as in its normal mode of functioning as …
combinational circuit is high during test mode as in its normal mode of functioning as …
A Novel Scan Architecture for Low Power Scan‐Based Testing
M Mojtabavi Naeini, CY Ooi - VLSI Design, 2015 - Wiley Online Library
Test power has been turned to a bottleneck for test considerations as the excessive power
dissipation has serious negative effects on chip reliability. In scan‐based designs, rippling …
dissipation has serious negative effects on chip reliability. In scan‐based designs, rippling …
On minimization of test power through modified scan flip-flop
S Ahlawat, JT Tudu - … Symposium on VLSI Design and Test …, 2016 - ieeexplore.ieee.org
Power dissipation during scan testing of modern high complexity designs could be many
folds higher than the functional operation power, which is a well established observation …
folds higher than the functional operation power, which is a well established observation …
Low power scan by partitioning and scan hold
E Arvaniti, Y Tsiatouhas - 2012 IEEE 15th International …, 2012 - ieeexplore.ieee.org
Scan testing dynamic power consumption can induce reliability problems in the circuit under
test (CUT) during manufacturing testing. In this paper, we propose a scan chain partitioning …
test (CUT) during manufacturing testing. In this paper, we propose a scan chain partitioning …
A novel technique to reduce both leakage and peak power during scan testing
S Kundu, S Chattopadhyay… - 2008 IEEE Region 10 and …, 2008 - ieeexplore.ieee.org
This paper addresses the issue of blocking pattern selection to reduce both leakage and
peak power consumption during circuit testing using scan-based approach. The blocking …
peak power consumption during circuit testing using scan-based approach. The blocking …
Modified scan architecture for an effective scan testing
K Paramasivam, K Gunavathi… - TENCON 2008-2008 …, 2008 - ieeexplore.ieee.org
Latest VLSI circuits face the problem of power dissipation not only in design phase but also
during testing phase. Power dissipation during testing may be increased up to three times …
during testing phase. Power dissipation during testing may be increased up to three times …
Modified low power scan based technique
MR Gowthami, G Harish, BVB Ram… - … Symposium on VLSI …, 2015 - ieeexplore.ieee.org
The testing power is the biggest concern in modern VLSI chip testing as the testing power is
very greater than the functional power which affects the reliability of the chip. In this paper …
very greater than the functional power which affects the reliability of the chip. In this paper …
Scan cell ordering for low power scan testing
Y Bonhomme, P Girard, C Landrault… - ETW: European Test …, 2002 - hal.science
Power consumption during scan testing is becoming a primary concern. In this paper, we
present a novel approach for scan cell ordering which significantly reduces the power …
present a novel approach for scan cell ordering which significantly reduces the power …
[PDF][PDF] Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits
N Nicolici, BM Al-Hashimi - Proceedings of the conference on Design …, 2000 - dl.acm.org
Power dissipated during test application is substantially higher than power dissipated during
functional operation [22] which can decrease the reliability and lead to yield loss. This paper …
functional operation [22] which can decrease the reliability and lead to yield loss. This paper …
Scan architecture modification with test vector reordering for test power reduction
C Giri, PK Choudhary… - … Symposium on Integrated …, 2007 - ieeexplore.ieee.org
Due to higher switching activity within scan chain for scanning in/out of the vector/response
pair, during testing average and peak power dissipation is much higher than the normal …
pair, during testing average and peak power dissipation is much higher than the normal …