US20190244080A1 - Neural Network Processor with On-Chip Convolution Kernel Storage -
Google Patents US20190244080A1 - Neural Network Processor with On-Chip Convolution …

(57) ABSTRACT A parallel convolutional neural network is provided. The CNN is
implemented by a plurality of convolutional neural networks each on a respective …

Computer systems and methods optimize a secondary objec tive function in the training of a
multi-layer feed-forward neural network in which the secondary objective is a func tion of the …

A method of address translation of images and filters to Vir tual matrices to perform a
convolution by matrix multiplica tion includes receiving an image and a filter. Each image …

(57) ABSTRACT A distributed deep neural net (DNN) utilizing a distributed, tile-based
architecture includes multiple chips, each with a central processing element, a global …

Described herein are techniques for training deep neural networks (DNNs) using an
alternating direction method of multipliers (ADMM) algorithm. The DNNs may be trained to …

BACKGROUND [0001] Embodiments of the present disclosure relate to a hardware
accelerator for parallel and distributed tensor computations, and more specifically, to neural …

Methods, systems, and apparatus, including computer programs encoded on computer
storage media, for training a convolutional neural network (CNN). The system includes a …

Techniques facilitating synchronization of processing engines for parallel deep learning are
provided. In one example, a first processing component associated with a processor and …

Techniques in advanced deep learning provide improvements in one or more of accuracy,
performance, and energy efficiency. An array of processing elements performs flow-based …