16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS

K Yang, D Fick, MB Henry, Y Lee… - … Solid-State Circuits …, 2014 - ieeexplore.ieee.org
True random number generators (TRNGs) use physical randomness as entropy sources and
are heavily used in cryptography and security [1]. Although hardware TRNGs provide …

Graphene: Strong yet lightweight row hammer protection

Y Park, W Kwon, E Lee, TJ Ham… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Row Hammer is a serious security threat to modern computing systems using DRAM as
main memory. It causes charge loss in DRAM cells adjacent to a frequently activated …

A novel circuit design of true random number generator using magnetic tunnel junction

Y Wang, H Cai, LAB Naviner, JO Klein… - 2016 IEEE/ACM …, 2016 - ieeexplore.ieee.org
Random numbers are widely used in the cryptography and security systems. However, most
of the true random number generators (TRNG) which use physical randomness are with …

TROT: A three-edge ring oscillator based true random number generator with time-to-digital conversion

M Grujić, I Verbauwhede - … on Circuits and Systems I: Regular …, 2022 - ieeexplore.ieee.org
This paper introduces a new true random number generator (TRNG) based on a three-edge
ring oscillator. Our design uses a new technique with a time-to-digital converter to effectively …

Dsac: Low-cost rowhammer mitigation using in-dram stochastic and approximate counting algorithm

S Hong, D Kim, J Lee, R Oh, C Yoo, S Hwang… - arXiv preprint arXiv …, 2023 - arxiv.org
DRAM has scaled to achieve low cost per bit and this scaling has decreased Rowhammer
threshold. Thus, DRAM has adopted Target-Row-Refresh (TRR) which refreshes victim rows …

ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates

PJ Nair, DH Kim, MK Qureshi - ACM SIGARCH Computer Architecture …, 2013 - dl.acm.org
DRAM scaling has been the prime driver for increasing the capacity of main memory system
over the past three decades. Unfortunately, scaling DRAM to smaller technology nodes has …

Architectural support for mitigating row hammering in DRAM memories

DH Kim, PJ Nair, MK Qureshi - IEEE Computer Architecture …, 2014 - ieeexplore.ieee.org
DRAM scaling has been the prime driver of increasing capacity of main memory systems.
Unfortunately, lower technology nodes worsen the cell reliability as it increases the coupling …

True random number generator circuits based on single-and multi-phase beat frequency detection

Q Tang, B Kim, Y Lao, KK Parhi… - Proceedings of the IEEE …, 2014 - ieeexplore.ieee.org
A fully-digital True Random Number Generator (TRNG) measures the frequency difference
between two free-running ring oscillators, or in other words the beat frequency, to extract …

Reducing DRAM latency via charge-level-aware look-ahead partial restoration

Y Wang, A Tavakkol, L Orosa, S Ghose… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Long DRAM access latency is a major bottleneck for system performance. In order to access
data in DRAM, a memory controller (1) activates (ie, opens) a row of DRAM cells in a cell …

Special session: Reliability analysis for AI/ML hardware

S Kundu, K Basu, M Sadi, T Titirsha… - 2021 IEEE 39th VLSI …, 2021 - ieeexplore.ieee.org
Artificial intelligence (AI) and Machine Learning (ML) are becoming pervasive in today's
applications, such as autonomous vehicles, healthcare, aerospace, cybersecurity, and many …