Performance analysis of the impact of design parameters to network-on-chip (NoC) architecture

NY Phing, MN Mohd Warip, P Ehkan… - Recent Trends in …, 2018 - Springer
Abstract Network-on-Chip (NoC) also known as on-chip interconnection network has been
proposed as a solution to System-on-Chip (SoC). The routing algorithm and topology are …

Comparative Performance Analysis of Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based Network-On-Chip

MS Saliu, MO Momoh, PU Chinedu… - … -Journal of Electrical …, 2021 - elektrika.utm.my
Abstract Network-on-Chip (NoC) has been proposed as a viable solution to the
communication challenges on System-on-Chips (SoCs). As the communication paradigm of …

[PDF][PDF] Performance comparison of XY, OE and DY Ad routing algorithm by load variation analysis of 2-dimensional mesh topology based network-on-chip

P Parandkar, JK Dalal, S Katival - BIJIT Journal, 2012 - bvicam.in
Network on chip is a scalable and flexible communication architecture for the design of core
based System-on-Chip. Communication performance of a NOC heavily depends on routing …

[PDF][PDF] Area Efficient Design of Routing Node for Network-on-Chip

R Maroofi, V Nitnaware, S Limaye - International Journal of Computer …, 2011 - Citeseer
Abstract Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication
demands of future Systems-on-Chip (SoC). The main components of an NoC are the …

A study of network-on-chip performance

V Bhaskar - Proceedings of the 2021 Thirteenth International …, 2021 - dl.acm.org
Network-on-Chip (NoC) technology was introduced by incorporating the concepts of
computer networks for on-chip communication. The packet based communication has …

Performance evalulation of different routing algorithms in Network on Chip

JK Singh, AK Swain, TNK Reddy… - 2013 IEEE Asia Pacific …, 2013 - ieeexplore.ieee.org
Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on
Chip (SoC). By the developments achieved in integrated circuits (IC) manufacturing there …

Topology design of extended torus and ring for low latency network-on-chip architecture

NY Phing, MNM Warip, P Ehkan… - TELKOMNIKA …, 2017 - telkomnika.uad.ac.id
Abstract In essence, Network-on-Chip (NoC) also known as on-chip interconnection network
has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm …

[PDF][PDF] DL (2m): A New Scalable Interconnection Network for System-on-Chip.

Y Liu, J Han, H Du - J. Comput., 2009 - Citeseer
With the feature size of semiconductor technology reducing and intellectual properties (IP)
cores increasing, on chip communication architectures have a great influence on the …

A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison

K Gaffour, MK Benhaoua, AH Benyamina… - International Journal of …, 2023 - Taylor & Francis
Network on-Chip (NoC) is scalable, flexible, modular communication structure for Multi/Many-
core architectures. It allows simpler interconnect models with higher bandwidth compared to …

An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

R Poovendran, S Sumathi - Concurrency and computation …, 2019 - Wiley Online Library
The incorporation of network‐on‐Chip with communication delivers a strengthening solution
to the rising complexity and problems in system‐on‐chip. Here, mesh topology is shortly …