Highly-linear voltage-to-time converter (VTC) circuit for time-based analog-to-digital converters (T-ADCs)

H Mostafa, YI Ismail - 2013 IEEE 20th international conference …, 2013 - ieeexplore.ieee.org
Time-based ADC is an essential block in designing software radio receivers because it
exhibits higher speed and lower power compared to the conventional ADC, especially, at …

A new design methodology for voltage-to-time converters (VTCs) circuits suitable for time-based analog-to-digital converters (T-ADC)

MW Ismail, H Mostafa - 2014 27th IEEE International System …, 2014 - ieeexplore.ieee.org
Voltage-to-Time Converter (VTC) circuit is considered one of the essential blocks in the
design of Time-based Analog-to-Digital Converters (T-ADCs). T-ADC is a promising …

Time-interleaved single-slope ADC using counter-based time-to-digital converter

HT Choi, YH Kim, KS Kim, J Kim… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
In this paper, a time-domain analog-to-digital converter (ADC) using time-to-digital converter
(TDC) is presented. The use of TDC in ADCs is a promising technique for future scaled …

A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

KA Townsend, AR Macpherson… - Proceedings of 2010 …, 2010 - ieeexplore.ieee.org
This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter
(ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital …

A 5GS/s voltage-to-time converter in 90nm CMOS

AR Macpherson, KA Townsend… - 2009 European …, 2009 - ieeexplore.ieee.org
A voltage-to-time converter (VTC) is presented for use in a time-based analog-to-digital
converter (ADC). The converter runs with a 5 GHz input clock to provide a maximum …

A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters

H Pekau, A Yousif, JW Haslett - 2006 IEEE International …, 2006 - ieeexplore.ieee.org
A novel 0.13 mum CMOS integrated linear voltage to pulse delay time converter (VTC) is
proposed. The VTC architecture uses current starved inverters where the inverter delay …

A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18- CMOS

LJ Chen, SI Liu - IEEE Transactions on Very Large Scale …, 2015 - ieeexplore.ieee.org
Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-μm CMOS
process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a …

A high linear voltage-to-time converter (VTC) with 1.2 V input range for time-domain analog-to-digital converters

H Liu, M Liu, Z Zhu, Y Yang - Microelectronics Journal, 2019 - Elsevier
This paper presents a high linear voltage-to-time converter (VTC) with wide input range of
over 1.2 V pp, diff for the high-speed high-linear time-domain (TD) analog-to-digital …

An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS

T Watanabe, T Terasawa - 2009 16th IEEE International …, 2009 - ieeexplore.ieee.org
An analog-to-digital and time-to-digital converter using a common architecture (Time A/D
converter TAD) is presented. Its resolutions for both analog-to-digital converter (ADC) mode …

A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element

V Dhanasekaran, M Gambhir… - … Solid-State Circuits …, 2009 - ieeexplore.ieee.org
Low-power, small-area, 20MHz-BW ADCs that can be integrated in nanoscale CMOS
technologies are of immense interest to the wireless communication industry …