This paper describes a comprehensive approach for using the memory controller to improve
DRAM energy efficiency and manage DRAM power. We make three contributions:(1) we …

DRAMs require periodic refresh for preserving data stored in them. The refresh interval for
DRAMs depends on the vendor and the design technology they use. For each refresh in a …

While there have been several studies and proposals for energy conservation for CPUs and
peripherals, energy optimization techniques for selective operating mode control of DRAMs …

Owing to increasing demand of faster and larger DRAM system, the DRAM system accounts
for a large portion of the total power consumption of computing systems. As memory traffic …

Previous work on DRAM power-mode management focused on hardware-based techniques
and compiler-directed schemes to explicitly transition unused memory modules to low …

We re-think DRAM power modes by modeling and characterizing inter-arrival times for
memory requests to determine the properties an ideal power mode should have. This …

The widespread use of multicore processors has dramatically increased the demand on
high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to …

Existing techniques manage power for the main memory by passively monitoring the
memory traffic, and based on which, predict when to power down and into which low-power …

Energy consumption has become a major constraint on the capabilities of computer
systems. In large systems the energy consumed by Dynamic Random Access Memories …

Scaling DRAM below 20nm has become a major challenge due to intrinsic limitations in the
structure of a bit cell. Future DRAM chips are likely to suffer from significant variations and …