While architects understand how to build cost-effective parallel machines across a wide
spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real …

Multithreaded processor architectures are becoming increasingly commonplace: many
current and upcoming designs support chip multiprocessing, simultaneous multithreading …

While there have been many recent proposals for hardware that supports Thread-Level
Speculation (TLS), there has been relatively little work on compiler optimizations to fully …

As increasing the performance of single-threaded processors becomes increasingly difficult,
consumer desktop processors are moving toward multi-core designs. One way to enhance …

Thread-level speculation (TLS) allows us to automatically parallelize general-purpose
programs by supporting parallel execution of threads that might not actually be independent …

As multi-core architectures with Thread-Level Speculation (TLS) are becoming better
understood, it is important to focus on TLS compilation. TLS compilers are interesting in that …

As we look to the future, and the prospect of a billion transistors on a chip, it seems
inevitable that microprocessors will exploit having multiple parallel threads. To achieve the …

In this paper, we provide examples of how thread-level speculation (TLS) simplifies manual
parallelization and enhances its performance. A number of techniques for manual …

With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed
are aggressively executed in parallel. If the hardware detects a cross-thread dependence …

Thread-level speculation (TLS) makes it possible to parallelize general purpose C
programs. This paper proposes software and hardware mechanisms that support …